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June 2003
Datasheet
DMR01
Low Power Digital Multichannel Receiver
FEATURES
* * * * * * * * * LOW COST MICRO POWER DESIGNED FOR DBPSK CODED DATA ERROR CORRECTING DECODER DIFFERENT TRANSMIT FREQUENCIES UNLICENSED FREQUENCY BAND DIFFERENT DATA RATES SHORT RANGE APPLICATIONS (up to 3m/10ft) TSSOP20 PACKAGE
APPLICATIONS
* * * * * * * BATTERY POWERED SYSTEMS WIRELESS DATA TRANSMISSION ACCESS CONTROL ALARM FUNCTIONS WIRELESS INTERFACE REMOTE CONTROL WIRELESS TRANSMISSIONS THROUGH CONDUCTING FLUIDS
General Description
The DMR01 is a micro power receiver chip for low frequency data transmission systems. Based on a 32 kHz clock source, 8 different carrier frequencies from 8.192 kHz to 122.88 kHz are possible (fcr = (2n+1) x 8192 Hz, n = 0..7). Depending on the transmit distance and the transmit time, the DMR01 works with 4 different data rates from 1 to 8 kBaud. The DMR01 is able to receive coded data until with a maximum length of 128 bit for each transmit package. A frame detector gives the possibility to separate the data for different applications. The DMR01 uses a serial SPI register for a simple data exchange with external microcontrollers. Features like input amplifier gain, ADC sensitivity, data rate, selection of coded or uncoded data are programmable via the SPI interface.
Block Diagram
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Datasheet_DMR01 June 2003
Electrical Specifications
AC / DC Characteristics @ VDD = 3.3V ,TA = 25C unless otherwise specified
PARAMETER
INPUT RECEIVER BANDWIDTH BW0 = 0 BW0 = 1 DATA RATE Br = 00 Br = 01 Br = 10 Br = 11 INPUT @ BW0 = 1 Input Bias Voltage Input Impedance Voltage Gain (@ GA = 00) Voltage Gain (@ GA = 01) Voltage Gain (@ GA = 10) Voltage Gain (@ GA = 11) INPUT @ BW0 = 0 Input Bias Voltage Input Impedance Voltage Gain (@GA = 00) Voltage Gain (@GA = 01) Voltage Gain (@GA = 10) Voltage Gain (@GA = 11) PREAMPLIFIER NOISE @ BW0 = 1 Spectral Noise Voltage referred to Input (RMS) Broadband Output Noise PREAMPLIFIER NOISE @ BW0 = 0 Spectral Noise Voltage referred to Input (RMS) Broadband Output Noise POWERUP TIME RECEIVER WAKE-UP TIME
CONDITION
MIN
TYP
10 130 1024 2048 4096 8192
MAX
UNITS
kHz kHz Bit/s Bit/s Bit/s Bit/s
small signal
0.95 271 55 49 43 35 0.95 287 55 49 43 35
1.35 315 67 61 55 47 1.28 340 69 63 57 49 77 165 213 193
1.90 370 70 64 58 50 1.75 410 70 64 58 50
V k dB dB dB dB V k dB dB dB dB nV/ Hz mV nV / Hz mV
small signal
@100kHz 1Hz - 1 MHz @ 10kHz 1Hz - 1 MHz
100 100 SPI-INTERFACE (Sin, Sout, Sck) Logical low level Logical high level Clock frequency Clock high time Clock low time Rise time (Clock) Fall time (Clock) Data input setup time Data input hold time Chip select setup time Chip select hold time POWER SUPPLY @ BW0 = 1 Standby current (Rec on = 0) Operating current (Rec on = 1) POWER SUPPLY @ BW0 = 0 Standby current (Rec on = 0) Operating current (Rec on = 1) TEMPERATURE Specified range No load, no clock fClk =32kHz No load, no clock fClk =32kHz -20 1 56 1 43 27 5 105 5 90 60 0.3VDD 0.7VDD 5 80 80 10 10 5 5 10 10
s s V V MHz ns ns ns ns ns ns ns ns
A A A A C
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Datasheet_DMR01 June 2003
Absolute maximum ratings
PARAMETER
Supply Voltage Voltage @ all Inputs and Outputs Pins ESD protection on all pins Current @ all Input and Output Pins Operating Temperature Storage Temperature Soldering Temperature 10 seconds -20 -65
CONDITION
MIN
2.5 VSS-0.3
TYP
3.6 1
MAX
5.5 VDD+0.3 10 85 150 250
UNITS
V V kV mA C C C
Pin Configuration
TSSOP20 package
Pin #
ANAIN CMPIN AVSS RECON DVSS RESB F32K IRQB DVSS CKOUT ANATST AVDD NC TESTB
Name
ANAIN CMPIN AVSS RECON DVSS RESB F32K IRQB DVSS CLKOUT DOUT DVDD SCK SIN SOUT CSB TESTB NC AVDD ANATST
Description
RF input signal Level detect input Analog Ground Power for external circuit Digital ground Reset Input for external clock Interrupt (valid data received) Digital ground Clock for uncoded data Uncoded data output Digital supply voltage Serial data clock for SPI Serial data input for SPI Serial output for SPI Chip select Test pin Not connected Analog supply voltage Test pin (output)
DMR01
CSB SOUT SIN SCK DVDD DOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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Datasheet_DMR01 June 2003
Module Description
Input Amplifier and A/D Conversion
Fig. 2 shows a block diagram of the input stage. The input stage consists of an input amplifier, a flash A/D-converter and a comparator for high energy detection of the input signal. The input amplifier has a gain of about 2'000 which simplifies external circuitry. The A/D-converter has a resolution of 4 Bit and converts the input signal into a signed 4 bit word within less than 1s. Sampling frequency is 32'768 Hz. To save power in stand by mode the analog input stage can be switched of (`RecOn'). The comparator detects high level input signals on it's input Cmpin. This input is normally connected directly to the receiving antenna. Due to the modulation technique, there will always be a number of sinusoidal waves per transmitted bit. The output of the comparator enters therefore a counter (located in the interface part) which counts the number of waves with high energy. At the end of a transmission the value of this counter gives an information about the energy level of the received data stream. This feature is used to detect if a transmitter is located very close to the receiving antenna.
Bit Estimator
Fig. 3 shows a block diagram of the bit estimator. The bit estimator uses a very sophisticated and efficient algorithm to estimate incoming data out of the 4 bit information of the A/D-converter. It is designed to work with phase modulated input signals. More precisely, the modulation technique is differential binary phase shift keying (DBPSK). This means that there is a phase shift of 180 with every transmitted logic 1. Depending on the programmed baud rate the estimator expects 1, 2, 4 or 8 sinusoidal waves per bit for baud rates of 8'192, 4'096, 2'048 or 1'024 bit/s. The estimator is also able to detect the signal energy. `Aqual' is high if the estimated bit `Aest' has an energy level of more than programmed in `BitQLevel'. `Aest' and `Aqual' are updated with the negative edge of `Clka'. To save power in stand by mode the bit estimator can be switched off (`RecOn').
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Datasheet_DMR01 June 2003
Frame Detector
Fig. 4 shows a block diagram of the frame detector. It's function is to detect a special string in the incoming data stream of `Aest' / `Clka'. The string which will be detected can be programmed with the 12 bit input word `Frame'. The detector accepts an incoming string as start frame if a certain number of bits (`FrmQLevel') of the incoming frame word have a high energy level (`Aqual' = 1) and a certain number of bits (`NoOfMatch') matche the frame word `Frame'. In this case the signal `FMatch' will be change from low to high and the following input bits (`Aest' / `Clka') will be connected to `Best' / 'Clkb'. `Best' is updated with the negative edge of `Clkb' and the detector will not recognize any other strings until the `Fclr' input is set to `1'. `Fclear' is controlled by the interface. It resets the detector if transmission is finished. The frame detection function can be disabled (`Fdeton' = 0). In this case the decoder will also not work and `Best', `Clkb' remains 0.
Decoder
Fig. 5 shows a block diagram of the decoder. It decodes a convolutional code with rate 1/2 using a polynomial function. The incoming bits are grouped in pairs of 2 bits whereas Cest the first one is the code bit and the second one is the original data bit. The threshold decoder decodes these Clkc set of pairs into a data stream appearing at `Cest' / `Clkc'. Data will be updated on the negative edge of `Clkc'. The decoding procedure will be started with a high level at `Fmatch'. It is also possible to disable the decoding function. If `Decode' is low the decoder will map `Best' / `Clkb' to `Cest' / `Clkc' if Fmatch is high.
A
Best Clkb
Code- and Databit Separator
Enable
Di Ci
Syndromgenerator Majority Decision
Enable
Mux
Y
Clks
B
Fmatch Decode Fig.5: Decoder
A/B
Interface
Fig. 7 shows the block diagram of the Interface. The interface has different functions: Communication with a microprocessor (SPI-interface) Saving all register values for programming Saving incoming data Interrupt function Counting pulses for high input energy detection
Additionally the interface also handles the end of a transmission. The first 4 incoming bits (MSB first) after the low to high transition of `Fmatch' define the number of bytes the currently transmitted block will have. The interface resets the frame detector exactly after this number of bytes is stored. An interrupt will be generated after completion of transmission (IRQ changes to low) and a request flag is set in the interrupt register. A counter counts the pulses from the comparator. The upper 8 bit of the 11bit counter can be read by the SPIinterface.
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Datasheet_DMR01 June 2003
Communication via SPI Interface
Each data transfer is initialized with a 8bit control word: Bit 7 Cmd2 Bit 6 Cmd1 Bit 5 Cmd0 Bit 4 Adr4 Bit 3 Adr3 Bit 2 Adr2 Bit 1 Adr1 Bit 0 Adr0
Cmd2...Cmd0 represent the command word and define the action. Adr4..Adr0 is the address which will be accessed. The following commands are possible: Cmd2 0 0 0 0 1 1 1 1 Cmd1 0 0 1 1 0 0 1 1 Cmd0 0 1 0 1 0 1 0 1 Action Not defined Read register (address 00 to 07H) Read YCUML (only for test) Read YCUMH (only for test) Read incoming data (address 00 to 11H) Write register (address 00 to 07H) Read ZINTL (only for test) Read ZINTH (only for test)
Each data transfer starts with a command and a corresponding address. Communication is initialized with the falling edge of CS. There is an auto increment function implemented for read and write operation. This means that the command word is necessary only once for consecutive addresses. The MSB (most significant bit, bit7) has to be set first in write operation and will be present first in read operation. Data at `Sin' is sampled with the positive edge of `Sck' whereas Data at `Sout' will be updated with the negative edge of `Sck'.
Bus Timing
Write Sequence
Fig.8 shows the write timing. In this case the command word is "write register (address 00H)". The value which is stored in this register is AAH.
Read Sequence
Fig.9 shows the read timing. In this case the command word is "read register (address 00H)". The value which is clocked at `Sout' is AAH.
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Datasheet_DMR01 June 2003
Registers for DMR01 configuration
The system consists of several registers for programming the desired function. All registers will be reset to 0 with `Res' = `0'.
Control register
Register name: Access: Description: Bit 7 Out1 Description: Bit 6 Out0 CNT R/W Control register for programming the function of the DMR-01 Bit 5 Br1 Out1,Out0 = Bit 4 Br0 Bit 3 Dec on Bit 2 Fdet on Bit 1 Rec on Bit 0 Address 00H
00 : no internal signals available at Pin `Datout' and Pin `Clkout' 01 : `Aest' is mapped to `Datout', `Clka' is mapped to `Clkout' 10 : `Best' is mapped to `Datout', `Clkb' is mapped to `Clkout' 11 : `Cest' is mapped to `Datout', `Clkc' is mapped to `Clkout' 00 : baud rate is set to 1'024 bit/s 01 : baud rate is set to 2'048 bit/s 10 : baud rate is set to 4'096 bit/s 11 : baud rate is set to 8'192 bit/s 0 : Decoder is not enabled 1 : Decoder is enabled 0 : Frame detector is off 1 : Frame detector is on 0 : Receiver is off (including input amplifier) 1 : Receiver is on
Br1,Br0 =
Dec on = Fdet on = Rec on =
In order to guarantee proper function `Rec on' must be set to `0' before any of Bit2 to Bit5 is changed.
Interrupt register
Register name: Access: Description: INT R/W (write access is only possible for IE) Interrupt status register
Bit 7 IRQ Description:
Bit 6
Bit 5
Bit 4
Bit 3 IE
Bit 2
Bit 1
Bit 0
Address 01H
IE = IRQ =
0 : Interrupt capability disabled 1 : Interrupt capability enabled 0 : Interrupt not requested 1 : Interrupt request after received data
An interrupt request will be reset by `Res' = `0' or by reading any of the data registers. In this case the positive edge of `CS' will trigger the clear function. This means that `CS' must be high to start the receiver again.
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Datasheet_DMR01 June 2003
Bit Quality level registers
Register name: Access: Description: High byte: Bit 7 BQL15 Low Byte: Bit 7 BQL7 Bit 6 BQL6 Bit 5 BQL5 Bit 4 BQL4 Bit 3 BQL3 Bit 2 BQL2 Bit 1 BQL1 Bit 0 BQL0 Address 03H Bit 6 BQL14 Bit 5 BQL13 Bit 4 BQL12 Bit 3 BQL11 Bit 2 BQL10 Bit 1 BQL9 Bit 0 BQL8 Address 02H BITQLEVELH (high byte) BITQLEVELL (low byte) R/W Bit quality level (energy level which represents good bit quality)
Frame quality level Register
Register name: Access: Description: FRMQLEVEL R/W Frame quality level (number of bits out of the 12 frame bits which must have an energy level which is higher than programmed in "Bit Quality level register" such that a frame is accepted) and number of matches (number of incoming bits which have to match the frame word) for acceptance. Bit 6 NOM2 Bit 5 NOM1 Bit 4 NOM0 Bit 3 FQL3 Bit 2 FQL2 Bit 1 FQL1 Bit 0 FQL0 Address 04H
Bit 7 NOM3
The numbers represented in FQL3..FQL0 and NOM3..NOM0 must be less or equal 12.
Frame registers
Register name: Access: Description: High byte: Bit 7 Low byte: Bit 7 FRM7 Bit 6 FRM6 Bit 5 FRM5 Bit 4 FRM4 Bit 3 FRM3 Bit 2 FRM2 Bit 1 FRM1 Bit 0 FRM0 Address 06H Bit 6 Bit 5 Bit 4 Bit 3 FRM11 Bit 2 FRM10 Bit 1 FRM9 Bit 0 FRM8 Address 05H FRAMEH (high byte) FRAMEL (low byte) R/W High Byte of the frame word
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Datasheet_DMR01 June 2003
Controlregister for analog part
Register name: Access: Description: ANACNTRL R/W Setup of analog part
Bit 7 GA1
Bit 6 GA0
Bit 5 BW0
Bit 4 ADR1
Bit 3 ADR0
Bit 2 CPS2
Bit 1 CPS1
Bit 0 CPS0
Address 07H
Description: CPS2,CPS1,CPS0: ADR1,ADR0:
This 3 Bits define the reference level of the comparator. "000" is Vdd/2. "111" means Vdd*15/16. 00 : Input range for A/D-converter is about +/- 0.4 * Vdd 01 : Input range for A/D-converter is about +/- 0.2 * Vdd 10 : Input range for A/D-converter is about +/- 0.1 * Vdd 11 : Input range for A/D-converter is about +/- 0.05 * Vdd 0 : 8 kHz Input Receiver Bandwidth Mode 1 : 122 kHz Input Receiver Bandwidth Mode 00 : Input amplifier voltage gain is about 2'000 01 : Input amplifier voltage gain is about 1'000 10 : Input amplifier voltage gain is about 500 11 : Input amplifier voltage gain is about 200
BW0 = GA1,GA0:
Cumulator output registers
Register name: Access: Description: High byte: Bit 7 YCUM15 Low byte: Bit 7 YCUM7 Bit 6 YCUM6 Bit 5 YCUM5 Bit 4 YCUM4 Bit 3 YCUM3 Bit 2 YCUM2 Bit 1 YCUM1 Bit 0 YCUM0 Address Bit 6 YCUM14 Bit 5 YCUM13 Bit 4 YCUM12 Bit 3 YCUM11 Bit 2 YCUM10 Bit 1 YCUM9 Bit 0 YCUM8 Address YCUMH (high byte) YCUML (low byte) R Output of the cumulator (only for test purposes)
These 2 registers are read by direct commands (see 5.7).
Statistic output registers
Register name: Access: Description: High byte: Bit 7 ZINT15 Low byte: Bit 7 ZINT7 Bit 6 ZINT6 Bit 5 ZINT5 Bit 4 ZINT4 Bit 3 ZINT3 Bit 2 ZINT2 Bit 1 ZINT1 Bit 0 ZINT0 Address Bit 6 ZINT14 Bit 5 ZINT13 Bit 4 ZINT12 Bit 3 ZINT11 Bit 2 ZINT10 Bit 1 ZINT9 Bit 0 ZINT8 Address ZINTH (high byte) ZINTL (low byte) R Statistic of the Bitestimator (only for test purposes)
These 2 registers are read by direct commands.
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Datasheet_DMR01 June 2003
Registers for data receiving
All data registers will be reset to 0 with `Res' = `0'.
Number of received Bytes
Register name: Access: Description: NOB R Number of received bytes - 1 of the last reception. If NOB is zero, then one byte of data was transmitted. Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 NOB3 Bit 2 NOB2 Bit 1 NOB1 Bit 0 NOB0 Address 00H
Bit 7 0
Data bytes
Access: Description: Bit 7 MSB Bit 6 R Received data. The end address depends on the message length (max. 10H) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Address 01H to 10H
High energy detector
Register name: Access: Description: ECOUNTER R Number of signal waves at the comparator input with high energy.
Bit 7 EC10
Bit 6 EC9
Bit 5 EC8
Bit 4 EC7
Bit 3 EC6
Bit 2 EC5
Bit 1 EC4
Bit 0 EC3
Address *
th
ECOUNTER represents the number of signal waves at the `Cmpin' input with a level higher than the reference value. Only every 8 clock is counted (positive edge triggered). *: The address of this register depends on the length of the received data stream. ECONTER is attached at the end of the message. ECOUNTER will be reset after reading data.
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Datasheet_DMR01 June 2003
Received data
Dataformat and Coding
Uncoded: 8 Bit 12 Bit 4 Bit Max. 128 Bit 0 Bit
Preamble
Coded: 8 Bit
Frameword
12 Bit
No.of Bytes
8 Bit
Data max. 16Bytes
Max. 256 Bit
Postamble
12 Bit
Fig. 10: Dataformat
For a proper function of the receiver, the transmitter has to do the correct function. First it is important to note the used dataformat as described in Fig. 8. Each datastream consists of a 8 bit preamble, a 12 bit frameword, a 4 bit information for the number of transmitted bytes, the data (up to 16 Bytes) and a postamble. A `0000' for the number of bytes means that 1 byte is transmitted. A '1111' means that 16 bytes are transmitted. For each bit, the transmitter must transmit a number of consecutive sinusoidal waves. This number is 8 for a baud rate of 1kbit/s, 4 for a baud rate of 2 kBit/s, 2 for a baud rate of 4 kbit/s and 1 for baud rate 8 kbit/s. The modulation technique is Differential Binary Phase Shift Keying (DBPSK). Therefore the phase of the sinusoidal waves has to be shifted by 180 if the bit (which actually should be transmitted) is logic high. The phase remains unchanged during transmission of this bit. If the coding function is used, the information has to be encoded according to a special function (not disclosed at the moment). Note that in case of coded transmissions only the data after the frameword has to be encoded. The postamble is necessary to bring the decoder to it's default state. Preamble and postamble should use an all one sequence('11...11') In case of uncoded transmission the postamble is not necessary. The encoder must be initialized with `000000' prior to every datastream.
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Datasheet_DMR01 June 2003
Package Information
TSSOP20
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Datasheet_DMR01 June 2003
MIN A A1 A2 D E1 E e L R R1 b b1 c c1 1 L1 aaa bbb ccc ddd e 2 3 Note : 1, 2
NOTES: 1. 2. 3. 4. 5.
NOM
MAX 1.10 0.15
NOTE
0.05 0.85 6.40 4.30 0.90 6.50 4.40 6.4 BSC 0.65 BSC 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF Issue : A 0.22 0.60
0.95 6.60 4.50 3, 8 4, 8
4.40 mm Body 0.65 mm Lead Pitch
0.75
0.30 0.25 0.20 0.16 8
5
BSC = Basic ...
ALL DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION 'D' DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION 'E1' DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. DIMENSION 'b' DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE 'b' DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07 MM FOR 0.5 MM PITCH PACKAGES. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. DATUMS -A - AND - B - TO BE DETERMINED AT DATUM PLANE - H DIMENSIONS 'D' ANO 'E1' ARE TO BE DETERMINED AT DATUM PLANE - H THIS DIMENSION APPLIES ONLY TO VARIATIONS WITH AN EVEN NUMBER OF LEADS PER SIDE. FOR VARIATION WITH AN ODD NUMBER OF LEADS PER SIDE, THE "CENTER" LEAD MUST BE COINCIDENT WITH THE PACKAGE CENTERLINE,. DATUM A.
6. 7. 8. 9.
10. ACROSS SECTION A - A TO BE DETERMINED AT 0.10 TO 0.25 MM FROM THE LEADTIP. 11. THIS VARIATION IS NOT REGISTERED WITH JEDEC.
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